(1) Field of the Invention
The present invention relates to an image forming apparatus, and in particular to a technology for simultaneously achieving high-speed processing and power saving by switching a clock frequency in a manner to prevent malfunction.
(2) Related Art
In recent years, an image forming apparatus is generally provided with a plurality of CPUs (Central Processing Units) for digitally controlling the components thereof. Furthermore, in order to meet the need for reducing the size of an image forming apparatus, the SoC (System on a Chip) is considered as a possible means for high-density packaging of a plurality of CPUs on a circuit substrate. When the SoC is employed, the increase in the scale of the integrated circuit causes degradation in yield, for example, which results in the increase in cost. In order to suppress the increase in cost by reducing the scale of the integrated circuit, peripheral circuits can be shared among the CPUs.
For example, instead of providing a dedicated clock supply circuit for each of the plurality of CPUs, the CPUs may use a single clock supply circuit in common. This reduces the number of clock supply circuits, and accordingly reduces the scale of the integrated circuit. Such a method is advantageous for, in particular, image forming apparatuses in a low price range such as SFPs (Single Function Peripherals) and AIO (All in One) printers, for which cost saving is strongly required.
In general, a digital circuit consumes less power when the clock frequency thereof is low, while the processing speed thereof is increased when the clock frequency is increased. With respect to an image forming apparatus, mechanical control processing can be performed at a low clock frequency because the processing load thereof is small. In contrast, image processing in color and other processing are preferably performed at a high clock frequency because the processing load thereof is large.
When a single clock supply circuit is shared between a CPU performing mechanical control (hereinafter, referred to as “mechanical control sub CPU”) and a CPU performing image processing (hereinafter, referred to as “image processing sub CPU”), the clock frequency of the clock supply circuit is switched between a higher clock frequency and a lower one. Specifically, the higher clock frequency is used during the image processing is performed, and the lower clock frequency is used while the image processing is not performed. This allows for both acceleration of the image processing and reduction in power consumed for the mechanical control processing.
However, in some cases, the mechanical control sub CPU counts clocks for determining timing in, for example, control processing of a position of a recording sheet. If this is the case, a problem may occur that the timing cannot be determined correctly if the clock frequency is changed while the mechanical control sub CPU is counting clocks. To avoid this problem, and also to accelerate the image processing, it is possible to perform the mechanical control also at a high clock frequency. However, in this case, power consumption cannot be saved.